A four-layer board

Stackup, inner-layer planes, controlled-impedance routing, stitching, and teardrops — the works, on a 40 × 25 mm board.

Click through the files — it's the whole project

A four-layer board — Visual Studio Code

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4 layers · ENIG stackup · planes · impedance · stitching

What's going on

layers: 4 in the constructor declares the copper; stackup(4, ...) finishes it — ENIG, dielectric constraints on for impedance work, and one prepreg thickness overridden from the JLCPCB defaults.
plane() reserves In1.Cu for ground and In2.Cu for 3V3. Planes are off-limits to the router — signals stay on the outer layers.
The signal trace asks the stackup what width hits 50 Ω ± 5 on F.Cu with impedanceWidth().
stitch('GND') fences the board edge with ground vias; teardrops() reinforces everything the router placed.

Build

terminal

cd my-project/hw
typecad-pcb build

Open build/four_layer.kicad_pcb in KiCAD — the stackup editor shows the dielectric table, the planes are there as filled zones, and DRC runs against the JLCPCB default rules.

Where to go next

Board Layout — stackup, planes, impedance, stitching, and teardrops in full
Routing — route options and the impedance constraint

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